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These instructions affect the condition flags, consequently the outcome can be tested using conditional branch instructions.
and_(regA, regB) AND i.e. regA AND regB
regA = regA & regB
if bit is set(1) in both regA and regB it will be set(1) in regA (bits are set(1) if they are set(1) in both arguments)
Note: non standard **and** instead of and is to avoid uPy interpreter treating it as a uPy keyword ... ref bug#753_
orr(regA,regB) OR i.e. regA OR regB
regA = regA | regB
if bit is set(1) in either regA or regB it will be set(1) in regA (bits are set(1) if either they are set(1) in either argument)
eor(regA, regB) XOR i.e. regA XOR regB
if bit is set(1) in either (but not both) of regA and regB will be set(1) in regA (bits are set(1) if they are DIFFERENT in the arguments)
mvn(regA, regB) move not - the contents of regA are replaced with the one's compliment of regB.
regA = 0xffffffff^regB
if bit is !set(1) in regB it will be set(1) in regA (bits are flipped 1=0 and 0=1)
bic(regA, regB) bit clear = regA = regA AND NOT regB This clears bits in regA by means of a mask in regB. I.E. if regB contains 101b, bits 0 and 2 of regA will be zeroed.
These instructions affect the condition flags and support full 32 bit registers
lsl(regA, regB[0-31]) logical shift left - shift regA left by regB bits
0 00000001 1 00000010 2 00000100 etc.
lsr(regA, regB[1-32]) logical shift right - shift regA right by regB bits
0 00000010 1 00000001 2 00000000 (bit permanently lost ... but maybe sets an overflow flag somewhere?)
asr(regA, regB[1-32]) arithmetic shift right - _just a right shift, same result as lsr unless the operand has the MSB set (negative number). In this case the sign bit is extended into the lower bits: hence a value of -20 subjected to an arithmetic right shift of 1 bit yields -10.
ror(regA, regB[1-31]) rotate right - rotate right brings rotated out set(1) bits in at the top of the register (32 bits)
0 00000000000000000000000000000010 1 00000000000000000000000000000001 2 10000000000000000000000000000000 (magic! we saved the bits life!)
clz(regA, regB) Count the leading zeros in regB and put the result in regA
rbit(regA, regB) Reverse the bits of the contents of regB and put the result in regA. Hence bit 0 of regA will hold the value of regB bit 31, bit 1 will hold regB bit 30, and so on.
Last edited by Peter Hinch, 2015-02-28 07:39:32