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An interesting article


There are 9 GPIO peripherals (A-I) each of which has a number (16?) of Pins which have general functions (Input, Output, ADC) and select special functions (SPI, DAC, PWM etc.?) ... the special functions available differ from Pin to Pin and may be determined here?

the GPIO peripheral base addresses


the GPIO peripheral offsets

GPIO_MODER Mode Register (32 bit), each pair of bits starting from the right-most pair as the lowest numbered associated Pin (i.e. bits 0 & 1 define mode for Pin 1, bits 2 & 3 for Pin 1 etc.) determines one of four general functions;

00 Input
01 General Purpose Output
10 Alternate Function
11 Analog

If a Pin is set to 0b10 (Alternative Function) either GPIO_AFR0 or GPIO_AFR1 (the Alternative Function Registers) can be used to read or set the specific alternative function (all Pins do not support all functions - refer the Pin map

GPIO_OTYPER Output Type Register (32 bit - but only lower 16 are used), each bit from the right represents the Output mode if the Pin is in Output mode (GPIO_MODER & <pin_mask> == 0b01);

0  Push/Pull output
1  Open Drain Ouput

GPIO_OSPEEDR Output Speed Register (32 bit), each pair of bits from the right represents the speed of a Pin (associated with a timer i.e. when it is doing pwm or similar, which implies it must be in an Alternative Function mode???);

00 2MHz low speed
01 25MHz medium speed
10 50MHz fast speed
11 100Mhz high speed

GPIO_PUPDR Pull Up or Down Register (32 bit) each pair of bits from the right set whether an Input mode Pin has a pull up or pull down resistor associated with it (saves some external components on using Pin as an Input);

00 no pu/pd resistor
01 pu resistor
10 pd resister
11 reserved #aka unused ... possibly indeterminate behaviour?                                               

GPIO_IDR Input Data Register (32 bit - but only lower 16 are used - Read Only) each bit, from the right, indicates for corresponding Pin that is in Input mode, whether the Input signal is high (1/+ve) or low (0/Gnd);

0  high
1  low

when pyb.LED(4).intensity(val) the corresponding bit(4) in stm.GPIOB+stm.GPIO_IDR when sampled may return either low or high, presumably because it is getting input from Timer 3 Channel 1

GPIO_ODR Output Data Register (32 bit - but only lower 16 are used) each bit, from the right, can be used to set the corresponding Pin (if it is in Output mode) high (1/+ve) or low (0/Gnd) or read what state it is in, if it was previously set; When writing to this register you can set all the bits of the port at the same time to whatever you like. But if you only want to change one or several bits, you should consider using GPIO_BSRRL and GPIO_BSRRH instead.

0  high
1  low

GPIO_BSRRL Port Bit Set Reset Register Low (16 bit - Write Only) and GPIO_BSRRH Port Bit Set Reset Register High (16 bit - Write Only) are the lower and higher part of a 32-bit register that makes it safe to manipulate a single bit (Pin) or a subset of the port's bits, even when other parts of the port are used for different purposes. (This even includes the situation when some bits are controlled in a interrupt routine, while other bits are set/reset by a normal routine.)

Example: if you want to set bits 3 and 4 without influencing the other bits:

GPIO_BSRRL 0b0000000000011000 set a ports Output Data Register Bits

If you want to reset bit 4, again without influencing any other bit in the port:

GPIO_BSRRH 0b0000000000010000 resets a ports Output Data Register Bit

GPIO_LCKR Configuration Lock Register (32 bit - but only lower 17 are used) used to lock the configuration of a port until next reset. Lower 16 bits indicate (1) which Pin configurations are locked and bit 16 is used in a Configuration Lock Sequence to lock the pins;

  1. Set bits 0 through 15 of the register indicating which pins should have their configuration locked 2.Set LCKK (bit 16) to 1 and write the value into the register
  2. Set LCKK (bit 16) to 0 and write the value into the register
  3. Set LCKK (bit 16) to 1 and write the value into the register
  4. Read the lock bit of the port

GPIO_AFR0 Alternative Function Register 0 (32 bit) GPIO_AFR1 Alternative Function Register 1 (32 bit) Each 4 bits in these registers, starting from the left most 4 in AFR0 and spilling over into GPIO_AFR1 (for the higher-numbered 8 pins) indicates or sets (if GPIO_MODER is set to 0b10 'Alternative Function') for the corresponding Pin, what Alternative Function mode it is in;

0000 AF0  System
0001 AF1  TIM1/TIM2
0010 AF2  TIM3..5
0011 AF3  TIM8..11
0100 AF4  I2C1..3
0101 AF5  SPI1/SPI2
0110 AF6  SPI3
0111 AF7  USART1..3
1000 AF8  USART4..6
1001 AF9  CAN1/CAN2, TIM12..14
1010 AF10 OTG_FS, OTG_HS
1011 AF11 ETH
1101 AF13 DCMI
1110 AF14 

refer the Pin map for Pin capabilities.