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Reference Getting Started with the STM32F4 and GCC


Switch on and off the link between on-chip peripherals and the hardware and peripheral clocks - a power saving measure(?) - each clock is controlle dby a pair of set/reset registers (setting a bit in an ENR register enables the clock for the corresponding peripheral, setting a bit in an STR register disables it).

  • AHB indicates Hardware clock
  • APB indicates Peripheral clock

the Reset & Clock Control base address

RCC - only one.

the Reset & Clock Control offsets

pyboard bitmask constants module

RCC_CR Control Register (32 bit)

RCC_PLLCFGR PLL (Programmable Logic Level???) Configuration Register (32 bit)

RCC_PLLI2SCFGR PLL (Programmable Logic Level???) I2S (Bus) Configuration Register (32 bit)

RCC_CFGR Clock Configuration Register (32 bit)

RCC_CIR Clock Interrupt Register (32 bit)

RCC_BDCR Backup Domain Control Register (32 bit)

RCC_SSCGR Spread Spectrum Clock Generation Register (32 bit)

RCC_AHB1ENR, RCC_AHB2ENR & RCC_AHB3ENR AHBx Peripheral Clock Registers (32 bit)

RCC_AHB1RSTR, RCC_AHB2RSTR & RCC_AHB3RSTR AHBx Peripheral Reset Registers (32 bit)

RCC_APB1RSTR & RCC_APB2RSTR APBx Peripheral Reset Registers (32 bit)

RCC_APB1ENR & RCC_APB2ENR APBx Peripheral Clock Enable Registers (32 bit)

RCC_AHB1LPENR, RCC_AHB2LPENR & RCC_AHB3LPENR AHBx Peripheral Clock Enable in Low Power Mode Registers (32 bit)

RCC_APB1LPENR & RCC_APB2LPENR APBx Peripheral Clock Enable in Low Power Mode Registers (32 bit)