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and_(regA, regB) AND i.e. regA AND regB
python: regA = regA & regB
if bit is set(1) in both regA and regB it will be set(1) in regA (bits are set(1) if they are set(1) in both arguments)
Note: non standard **and** instead of and is to avoid uPy interpreter treating it as a uPy keyword ... ref bug#753_
orr(regA,regB) OR i.e. regA OR regB
python: regA = regA | regB
if bit is set(1) in either regA or regB it will be set(1) in regA (bits are set(1) if either they are set(1) in either argument)
eor(regA, regB) XOR i.e. regA XOR regB
python: regA=regA^regB
if bit is set(1) in either (but not both) of regA and regB will be set(1) in regA (bits are set(1) if they are DIFFERENT in the arguments)
mvn(regA, regB) move not - supposed to be a move operation?
python: regA = 0xffffffff^regB
if bit is !set(1) in regB it will be set(1) in regA (bits are flipped 1=0 and 0=1)
bic(regA, regB) bit clear = regA = regA AND NOT regB !!! hmmmmm, fathom that one later !!!!
appear to support full 32 bit registers
lsl(regA, regB[0-31]) logical shift left - shift regA left by regB bits
0 00000001
1 00000010
2 00000100 etc.
lsr(regA, regB[1-32]) logical shift right - shift regA right by regB bits
0 00000010
1 00000001
2 00000000 (bit permanently lost ... but maybe sets an overflow flag somewhere?)
asr(regA, regB[1-32]) arithmetic shift right - just a right shift, same result as lsr?
ror(regA, regB[1-31]) rotate right - rotate right brings rotated out set(1) bits in at the top of the register (32 bits)
0 00000000000000000000000000000010
1 00000000000000000000000000000001
2 10000000000000000000000000000000 (magic! we saved the bits life!)
Last edited by Peter Hinch, 2015-02-28 07:39:32