ADC - Analog to Digital Conversion
Reference
about
the ADC peripheral base addresses
ADC through ADC3
the ADC peripheral offsets
ADC_SR Status Register (32 bit)
AWD 0x00000001 0b0000000000000001 Analog watchdog flag
EOC 0x00000002 0b0000000000000010 End of conversion
JEOC 0x00000004 0b0000000000000100 Injected channel end of conversion
JSTRT 0x00000008 0b0000000000001000 Injected channel Start flag
STRT 0x00000010 0b0000000000010000 Regular channel Start flag
OVR 0x00000020 0b0000000000100000 Overrun flag
ADC_CR1* Control Register 1 (32 bit)
AWDCH 0x0000001F 0b00000000000000000000000000011111 [4:0] bits (Analog watchdog channel select bits)
EOCIE 0x00000020 0b00000000000000000000000000100000 Interrupt enable for EOC
AWDIE 0x00000040 0b00000000000000000000000001000000 AAnalog Watchdog interrupt enable
JEOCIE 0x00000080 0b00000000000000000000000010000000 Interrupt enable for injected channels
SCAN 0x00000100 0b00000000000000000000000100000000 Scan mode
AWDSGL 0x00000200 0b00000000000000000000001000000000 Enable the watchdog on a single channel in scan mode
JAUTO 0x00000400 0b00000000000000000000010000000000 Automatic injected group conversion
DISCEN 0x00000800 0b00000000000000000000100000000000 Discontinuous mode on regular channels
JDISCEN 0x00001000 0b00000000000000000001000000000000 Discontinuous mode on injected channels
DISCNUM 0x0000E000 0b00000000000000001110000000000000 [2:0] bits (Discontinuous mode channel count)
JAWDEN 0x00400000 0b00000000010000000000000000000000 Analog watchdog enable on injected channels
AWDEN 0x00800000 0b00000000100000000000000000000000 Analog watchdog enable on regular channels
RES 0x03000000 0b00000011000000000000000000000000 [2:0] bits (Resolution)
OVRIE 0x04000000 0b00000100000000000000000000000000 overrun interrupt enable
ADC_CR2 Control Register 2 (32 bit)
ADON 0x00000001 0b00000000000000000000000000000001 A/D Converter ON / OFF
CONT 0x00000002 0b00000000000000000000000000000010 Continuous Conversion
DMA 0x00000100 0b00000000000000000000000100000000 Direct Memory access mode
DDS 0x00000200 0b00000000000000000000001000000000 DMA disable selection (Single ADC)
EOCS 0x00000400 0b00000000000000000000010000000000 End of conversion selection
ALIGN 0x00000800 0b00000000000000000000100000000000 Data Alignment
JEXTSEL 0x000F0000 0b00000000000011110000000000000000 [3:0] bits (External event select for injected group)
JEXTEN 0x00300000 0b00000000001100000000000000000000 [1:0] bits (External Trigger Conversion mode for injected channelsp)
JSWSTART 0x00400000 0b00000000010000000000000000000000 Start Conversion of injected channels
EXTSEL 0x0F000000 0b00001111000000000000000000000000 [3:0] bits (External Event Select for regular group)
EXTEN 0x30000000 0b00110000000000000000000000000000 [1:0] bits (External Trigger Conversion mode for regular channelsp)
SWSTART 0x40000000 0b01000000000000000000000000000000 Start Conversion of regular channels
ADC_SMPR1 & ADC_SMPR2 Sample Time Registers (32 bit)
SMP10 0x00000007 0b00000000000000000000000000000111 [2:0] bits (Channel 10 Sample time selection)
SMP11 0x00000038 0b00000000000000000000000000111000 [2:0] bits (Channel 11 Sample time selection)
SMP12 0x000001C0 0b00000000000000000000000111000000 [2:0] bits (Channel 12 Sample time selection)
SMP13 0x00000E00 0b00000000000000000000111000000000 [2:0] bits (Channel 13 Sample time selection)
SMP14 0x00007000 0b00000000000000000111000000000000 [2:0] bits (Channel 14 Sample time selection)
SMP15 0x00038000 0b00000000000000111000000000000000 [2:0] bits (Channel 15 Sample time selection)
SMP16 0x001C0000 0b00000000000111000000000000000000 [2:0] bits (Channel 16 Sample time selection)
SMP17 0x00E00000 0b00000000111000000000000000000000 [2:0] bits (Channel 17 Sample time selection)
SMP18 0x07000000 0b00000111000000000000000000000000 [2:0] bits (Channel 18 Sample time selection)
ADC_JOFR1, ADC_JOFR2, ADC_JOFR3 & ADC_JOFR4 Injected Channel Data Offset Registers (32 bit)
JOFFSET1 0x0FFF 0b0000111111111111 Data offset for injected channel 1
ADC_HTR & ADC_LTR ADC Watchdog Higher/Lower Threshhold Registers (32 bit)
HT 0x0FFF 0b0000111111111111 Analog watchdog high threshold
LT 0x0FFF 0b0000111111111111 Analog watchdog low threshold
ADC_SQR1 Regular Sequence Register 1 (32 bit)
SQ13 0x0000001F 0b00000000000000000000000000011111 [4:0] bits (13th conversion in regular sequence)
SQ14 0x000003E0 0b00000000000000000000001111100000 [4:0] bits (14th conversion in regular sequence)
SQ15 0x00007C00 0b00000000000000000111110000000000 [4:0] bits (15th conversion in regular sequence)
SQ16 0x000F8000 0b00000000000011111000000000000000 [4:0] bits (16th conversion in regular sequence)
L 0x00F00000 0b00000000111100000000000000000000 [3:0] bits (Regular channel sequence length)
ADC_SQR2 Regular Sequence Register 2 (32 bit)
SQ7 0x0000001F 0b00000000000000000000000000011111 [4:0] bits (7th conversion in regular sequence)
SQ8 0x000003E0 0b00000000000000000000001111100000 [4:0] bits (8th conversion in regular sequence)
SQ9 0x00007C00 0b00000000000000000111110000000000 [4:0] bits (9th conversion in regular sequence)
SQ10 0x000F8000 0b00000000000011111000000000000000 [4:0] bits (10th conversion in regular sequence)
SQ11 0x01F00000 0b00000001111100000000000000000000 [4:0] bits (11th conversion in regular sequence)
SQ12 0x3E000000 0b00111110000000000000000000000000 [4:0] bits (12th conversion in regular sequence)
ADC_SQR3 Regular Sequence Register 3 (32 bit)
SQ1 0x0000001F 0b00000000000000000000000000011111 [4:0] bits (1st conversion in regular sequence)
SQ2 0x000003E0 0b00000000000000000000001111100000 [4:0] bits (2nd conversion in regular sequence)
SQ3 0x00007C00 0b00000000000000000111110000000000 [4:0] bits (3rd conversion in regular sequence)
SQ4 0x000F8000 0b00000000000011111000000000000000 [4:0] bits (4th conversion in regular sequence)
SQ5 0x01F00000 0b00000001111100000000000000000000 [4:0] bits (5th conversion in regular sequence)
SQ6 0x3E000000 0b00111110000000000000000000000000 [4:0] bits (6th conversion in regular sequence)
**ADC_JSQR Injected Sequence Register (32 bit
JSQ1 0x0000001F 0b00000000000000000000000000011111 [4:0] bits (1st conversion in injected sequence)
JSQ2 0x000003E0 0b00000000000000000000001111100000 [4:0] bits (2nd conversion in injected sequence)
JSQ3 0x00007C00 0b00000000000000000111110000000000 [4:0] bits (3rd conversion in injected sequence)
JSQ4 0x000F8000 0b00000000000011111000000000000000 [4:0] bits (4th conversion in injected sequence)
JL 0x00300000 0b00000000001100000000000000000000 [1:0] bits (Injected Sequence length)
ADC_JDR1 Injected Data Register 1 (32 bit)
ADC_JDR2 Injected Data Register 2 (32 bit)
ADC_JDR3 ADC Injected Data Register 3 (32 bit)
ADC_JDR4 Injected Data Register 4 (32 bit)
ADC_DR Regular Data Register (32 bit)
DATA 0x0000FFFF 0b00000000000000001111111111111111 Regular data
ADC2DATA 0xFFFF0000 0b11111111111111110000000000000000 ADC2 data