TIM - Timers
Reference
about
There are 14 Timers (1-14) each attached to one of two peripheral clocks, the speed of which is held in the last two values in pyb.freq().
Return the speed of a timer;
def tim_clockspeed(tim):
if tim in [1,8,9,10,11]:
return pyb.freq()[3]
elif tim in [2,3,4,5,6,7,12,13,14]:
return pyb.freq()[2]
else:
raise ValueError('Invalid timer number specified')
the Timer peripheral base addresses
TIM1 On Peripheral APB2 = Clock 2 = 84MHz = 84000000Hz = pyb.freq()[3]
TIM2 On Peripheral APB1 = Clock 1 = 42MHz = 42,000,000Hz = pyb.freq()[2]
TIM3 On Peripheral APB1 = Clock 1 = 42MHz = 42,000,000Hz = pyb.freq()[2]
TIM4 On Peripheral APB1 = Clock 1 = 42MHz = 42,000,000Hz = pyb.freq()[2]
TIM5 On Peripheral APB1 = Clock 1 = 42MHz = 42,000,000Hz = pyb.freq()[2]
TIM6 On Peripheral APB1 = Clock 1 = 42MHz = 42,000,000Hz = pyb.freq()[2]
TIM7 On Peripheral APB1 = Clock 1 = 42MHz = 42,000,000Hz = pyb.freq()[2]
TIM8 On Peripheral APB2 = Clock 2 = 84MHz = 84000000Hz = pyb.freq()[3]
TIM9 On Peripheral APB2 = Clock 2 = 84MHz = 84000000Hz = pyb.freq()[3]
TIM10 On Peripheral APB2 = Clock 2 = 84MHz = 84000000Hz = pyb.freq()[3]
TIM11 On Peripheral APB2 = Clock 2 = 84MHz = 84000000Hz = pyb.freq()[3]
TIM12 On Peripheral APB1 = Clock 1 = 42MHz = 42,000,000Hz = pyb.freq()[2]
TIM13 On Peripheral APB1 = Clock 1 = 42MHz = 42,000,000Hz = pyb.freq()[2]
TIM14 On Peripheral APB1 = Clock 1 = 42MHz = 42,000,000Hz = pyb.freq()[2]
the Timer peripheral offsets
pyboard Bitmask Constants Module
TIM_CR1 Control Register 1 (32bit) - a field-mask value, fields;
CEN 0x0001 0b0000000001 Counter enable
UDIS 0x0002 0b0000000010 Update disable
URS 0x0004 0b0000000100 Update request source
OPM 0x0008 0b0000001000 One pulse mode
DIR 0x0010 0b0000010000 Direction
CMS 0x0060 0b0001100000 CMS[1:0] bits (Center-aligned mode selection)
ARPE 0x0080 0b0010000000 Auto-reload preload enable
CKD 0x0300 0b1100000000 CKD[1:0] bits (clock division)
This is set to 1 on initialised timers, including LED4, toggling it on a generic timer with callback stops/starts the callback, setting it to zero on TIM3 with pwm running crashes the board ... but both pwm on LED(4) and callbacks on other times still run)
TIM_CR2 Control Register 2 (32 bit) - a field-mask value, fields;
CCPC 0x0001 0b000000000000001 Capture/Compare Preloaded Control
CCUS 0x0004 0b000000000000010 Capture/Compare Control Update Selection
CCDS 0x0008 0b000000000001000 Capture/Compare DMA Selection
MMS 0x0070 0b000000001110000 MMS[2:0] bits (Master Mode Selection)
TI1S 0x0080 0b000000010000000 TI1 Selection
OIS1 0x0100 0b000000100000000 Output Idle state 1 (OC1 output)
OIS1N 0x0200 0b000001000000000 Output Idle state 1 (OC1N output)
OIS2 0x0400 0b000010000000000 Output Idle state 2 (OC2 output)
OIS2N 0x0800 0b000100000000000 Output Idle state 2 (OC2N output)
OIS3 0x1000 0b001000000000000 Output Idle state 3 (OC3 output)
OIS3N 0x2000 0b010000000000000 Output Idle state 3 (OC3N output)
OIS4 0x4000 0b100000000000000 Output Idle state 4 (OC4 output)
TIM_SMCR Slave Mode Control Register (32 bit) - a field-mask value, fields;
SMS 0x0007 0b0000000000000111 SMS[2:0] bits (Slave mode selection)
TS 0x0070 0b0000000011100000 TS[2:0] bits (Trigger selection)
MSM 0x0080 0b0000000010000000 Master/slave mode
ETF 0x0F00 0b0000111100000000 ETF[3:0] bits (External trigger filter)
ETPS 0x3000 0b0011000000000000 ETPS[1:0] bits (External trigger prescaler)
ECE 0x4000 0b0100000000000000 External clock enable
ETP 0x8000 0b1000000000000000 External trigger polarity
Not found to be set on any investigated use case ...
TIM_DIER DMA/Interrupt enable register (32 bit) - a field-mask value, fields;
UIE 0x0001 0b000000000000001 Update interrupt enable
CC1IE 0x0002 0b000000000000010 Capture/Compare 1 interrupt enable
CC2IE 0x0004 0b000000000000100 Capture/Compare 2 interrupt enable
CC3IE 0x0008 0b000000000001000 Capture/Compare 3 interrupt enable
CC4IE 0x0010 0b000000000010000 Capture/Compare 4 interrupt enable
COMIE 0x0020 0b000000000100000 COM interrupt enable
TIE 0x0040 0b000000001000000 Trigger interrupt enable
BIE 0x0080 0b000000010000000 Break interrupt enable
UDE 0x0100 0b000000100000000 Update DMA request enable
CC1DE 0x0200 0b000001000000000 Capture/Compare 1 DMA request enable
CC2DE 0x0400 0b000010000000000 Capture/Compare 2 DMA request enable
CC3DE 0x0800 0b000100000000000 Capture/Compare 3 DMA request enable
CC4DE 0x1000 0b001000000000000 Capture/Compare 4 DMA request enable
COMDE 0x2000 0b010000000000000 COM DMA request enable
TDE 0x4000 0b100000000000000 Trigger DMA request enable
appears to affect calling of callback, first bit of both TIM_DIER and TIM_DMAR for a Timer must be set(1) for the callback to be called. When a Timer is initialised via uPy pyb module t4=pyb.Timer(4).init(freq=5) this fields value is initially 0, when a callback is initialised l4.callback(lambda t:pyb.LED(1).toggle()) it's set to 1. Can switch the callback on and off by setting this value e.g. Off: stm.mem32[stm.TIM4+stm.TIM_DIER]=0 and On: stm.mem32[stm.TIM4+stm.TIM_DIER]=1
TIM_SR Status Register (32bit - Read Only) - a field-mask value, fields;
UIF 0x0001 0b0000000000001 Update interrupt Flag
CC1IF 0x0002 0b0000000000010 Capture/Compare 1 interrupt Flag
CC2IF 0x0004 0b0000000000100 Capture/Compare 2 interrupt Flag
CC3IF 0x0008 0b0000000001000 Capture/Compare 3 interrupt Flag
CC4IF 0x0010 0b0000000010000 Capture/Compare 4 interrupt Flag
COMIF 0x0020 0b0000000100000 COM interrupt Flag
TIF 0x0040 0b0000001000000 Trigger interrupt Flag
BIF 0x0080 0b0000010000000 Break interrupt Flag
CC1OF 0x0200 0b0001000000000 Capture/Compare 1 Overcapture Flag
CC2OF 0x0400 0b0010000000000 Capture/Compare 2 Overcapture Flag
CC3OF 0x0800 0b0100000000000 Capture/Compare 3 Overcapture Flag
CC4OF 0x1000 0b1000000000000 Capture/Compare 4 Overcapture Flag
TIM_EGR Event Generation Register (32 bit) - a field-mask value, fields;
UG 0x01 0b00000001 Update Generation
CC1G 0x02 0b00000010 Capture/Compare 1 Generation
CC2G 0x04 0b00000100 Capture/Compare 2 Generation
CC3G 0x08 0b00001000 Capture/Compare 3 Generation
CC4G 0x10 0b00010000 Capture/Compare 4 Generation
COMG 0x20 0b00100000 Capture/Compare Control Update Generation
TG 0x40 0b01000000 Trigger Generation
BG 0x80 0b10000000 Break Generation
always returns zero, implying that it is used to send instructions to the MCU on if and how events are to be generated
TIM_CCMR1 Capture/Compare Mode register 1 (32 bit) - a field-mask value, the settings of some bit pairs (CC1S and CC2S) determine the meaning of the balance bits (there are two conflicting sets of masks defined for the balance bits);
Bit Block 1:
CC1S 0x0003 0b0000000000000011 [1:0] bits (Capture/Compare 1 Selection)
Depending on the value of CC1S the next 6 bits are either interpreted using these masks;
OC1FE 0x0004 0b0000000000000100 Output Compare 1 Fast enable
OC1PE 0x0008 0b0000000000001000 Output Compare 1 Preload enable
OC1M 0x0070 0b0000000001110000 [2:0] bits (Output Compare 1 Mode)
OC1CE 0x0080 0b0000000010000000 Output Compare 1 Clear Enable
Or these;
IC1PSC 0x000C 0b0000000000001100 [1:0] bits (Input Capture 1 Prescaler)
IC1F 0x00F0 0b0000000011110000 [3:0] bits (Input Capture 1 Filter)
Bit Block 2:
CC2S 0x0300 0b0000001100000000 [1:0] bits (Capture/Compare 2 Selection)
Depending on the value of CC2S the next 6 bits are either interpreted using these masks;
OC2FE 0x0400 0b0000010000000000 Output Compare 2 Fast enable
OC2PE 0x0800 0b0000100000000000 Output Compare 2 Preload enable
OC2M 0x7000 0b0111000000000000 [2:0] bits (Output Compare 2 Mode)
OC2CE 0x8000 0b1000000000000000 Output Compare 2 Clear Enable
Or these;
IC2PSC 0x0C00 0b0000110000000000 [1:0] bits (Input Capture 2 Prescaler)
IC2F 0xF000 0b1111000000000000 [3:0] bits (Input Capture 2 Filter)
TIM_CCMR2 Capture/Compare Mode Register 2 (32bit) - a field-mask value, the settings of some bit pairs (CC1S and CC3S and CC4S) determine the meaning of the balance bits (there are two conflicting sets of masks defined for the balance bits);
Bit Block 1:
CC3S 0x0003 0b0000000000000011 CC3S[1:0] bits (Capture/Compare 3 Selection)
Depending on the value of CC3S the next 6 bits are either interpreted using these masks;
OC3FE 0x0004 0b0000000000000100 Output Compare 3 Fast enable
OC3PE 0x0008 0b0000000000001000 Output Compare 3 Preload enable
OC3M 0x0070 0b0000000001110000 OC3M[2:0] bits (Output Compare 3 Mode)
OC3CE 0x0080 0b0000000010000000 Output Compare 3 Clear Enable
Or these;
IC3PSC 0x000C 0b0000000000001100 IC3PSC[1:0] bits (Input Capture 3 Prescaler)
IC3F 0x00F0 0b0000000011110000 IC3F[3:0] bits (Input Capture 3 Filter)
Bit Block 2:
CC4S 0x0300 0b0000001100000000 CC4S[1:0] bits (Capture/Compare 4 Selection)
Depending on the value of CC4S the next 6 bits are either interpreted using these masks;
OC4FE 0x0400 0b0000010000000000 Output Compare 4 Fast enable
OC4PE 0x0800 0b0000100000000000 Output Compare 4 Preload enable
OC4M 0x7000 0b0111000000000000 OC4M[2:0] bits (Output Compare 4 Mode)
OC4CE 0x8000 0b1000000000000000 Output Compare 4 Clear Enable
Or these;
IC4PSC 0x0C00 0b0000110000000000 IC4PSC[1:0] bits (Input Capture 4 Prescaler)
IC4F 0xF000 0b1111000000000000 IC4F[3:0] bits (Input Capture 4 Filter)
TIM_CCER Capture/Compare Enable Register (32 bit) - a field-mask value, fields;
CC1E 0x0001 0b000000000000001 Capture/Compare 1 output enable
CC1P 0x0002 0b000000000000010 Capture/Compare 1 output Polarity
CC1NE 0x0004 0b000000000000100 Capture/Compare 1 Complementary output enable
CC1NP 0x0008 0b000000000001000 Capture/Compare 1 Complementary output Polarity
CC2E 0x0010 0b000000000010000 Capture/Compare 2 output enable
CC2P 0x0020 0b000000000100000 Capture/Compare 2 output Polarity
CC2NE 0x0040 0b000000001000000 Capture/Compare 2 Complementary output enable
CC2NP 0x0080 0b000000010000000 Capture/Compare 2 Complementary output Polarity
CC3E 0x0100 0b000000100000000 Capture/Compare 3 output enable
CC3P 0x0200 0b000001000000000 Capture/Compare 3 output Polarity
CC3NE 0x0400 0b000010000000000 Capture/Compare 3 Complementary output enable
CC3NP 0x0800 0b000100000000000 Capture/Compare 3 Complementary output Polarity
CC4E 0x1000 0b001000000000000 Capture/Compare 4 output enable
CC4P 0x2000 0b010000000000000 Capture/Compare 4 output Polarity
CC4NP 0x8000 0b100000000000000 0Capture/Compare 4 Complementary output Polarity
This is set to 1 on TIM3 associated with pwm'able LED4, but set to 0 on generic initialised Timer's, set/unsetting it switches LED4 on/off .. has no affect on generic callback timers
TIM_CNT Counter Register (32bit) - the value the timer has counted to at the point in time it's read, can also be reset i.e. to restart the clock, interesting possibilities for setting in a callback?
TIM_PSC Prescalar Register (32 bit) holds the Timers Prescalar value, which coupled with TIM_ARR (it's Period) define the clocks frequency. Period, prescalar and source clock speed define the time it takes for timer to 'wrap' to zero (optionally triggering an interrupt).
Calculate appropriate prescalar and period values for any given frequency mimicking the C code in the pyb.Timer module source https://github.com/micropython/micropython/blob/master/stmhal/timer.c;
def calc(timer, freq):
if timer in [1,8,9,10,11]:
clk_speed = pyb.freq()[3]
elif timer in [2,3,4,5,6,7,12,13,14]:
clk_speed = pyb.freq()[2]
period = max(1, int(2 * clk_speed / freq))
prescalar = 1
while period > 0xffff:
period >>= 1
prescalar <<= 1
prescalar -= 1
period -= 1
return (prescalar, period)
TIM_ARR Auto Reload Register (aka PERIOD) (32 bit) - refer notes under TIM_PSC above.
TIM_RCR Repition Counter Register (32bit) not set in any investigated use case ...
TIM_CCR1, TIM_CCR2, TIM_CCR3, TIM_CCR4 Capture/Compare Registers 1-4 (32bit)
for LED4 attached to TIM3.TIM_CCR1 this controls the duty-cycle of the PWM signal
TIM_BDTR Break and Dead-Time Register (32 bit - Read Only) - a field-mask value, fields;
DTG 0x00FF 0b0000000011111111 [0:7] bits (Dead-Time Generator set-up)
LOCK 0x0300 0b0000001100000000 LOCK[1:0] bits (Lock Configuration)
OSSI 0x0400 0b0000010000000000 Off-State Selection for Idle mode
OSSR 0x0800 0b0000100000000000 Off-State Selection for Run mode
BKE 0x1000 0b0001000000000000 Break enable
BKP 0x2000 0b0010000000000000 Break Polarity
AOE 0x4000 0b0100000000000000 Automatic Output enable
MOE 0x8000 0b1000000000000000 Main Output enable
TIM_DCR DMA Control Register (32 bit) - a field-mask value, fields;
DBA 0x001F 0b0000000011111 DBA[4:0] bits (DMA Base Address)
DBL 0x1F00 0b1111100000000 DBL[4:0] bits (DMA Burst Length)
TIM_DMAR DMA Address for Full Transfer (DMA register for burst access) (32 bit) - a field-mask value, fields;
affects calling of callback, TIM_DIER = TIM_DMAR = 1 for callback to run, set to 1 when timer init'd (and not changed by uPy pyb module when callback attached);
- 1 - call callback?
- 0 - don't call callback?
TIM_OR Option Register (32 bit) - a field-mask value, fields;
TI4_RMP 0x00C0 0b000011000000 [1:0] bits (TIM5 Input 4 remap)
ITR1_RMP 0x0C00 0b110000000000 [1:0] bits (TIM2 Internal trigger 1 remap)