Timer (Tim) peripheral+offset field masks
TIM_CR1_CEN = 0b0000000000000001 #Counter enable
TIM_CR1_UDIS = 0b0000000000000010 #Update disable
TIM_CR1_URS = 0b0000000000000100 #Update request source
TIM_CR1_OPM = 0b0000000000001000 #One pulse mode
TIM_CR1_DIR = 0b0000000000010000 #Direction
TIM_CR1_CMS = 0b0000000001100000 #[1:0] Center-align mode select
TIM_CR1_ARPE = 0b0000000010000000 #Auto-reload preload enable
TIM_CR1_CKD = 0b0000001100000000 #[1:0] clock division
TIM_CR2_CCPC = 0b0000000000000001 #Captr/Cmpr Preloaded Control
TIM_CR2_CCUS = 0b0000000000000010 #Captr/Cmpr Control Update Sln
TIM_CR2_CCDS = 0b0000000000001000 #Captr/Cmpr DMA Selection
TIM_CR2_MMS = 0b0000000001110000 #[2:0] Master Mode Selection
TIM_CR2_TI1S = 0b0000000010000000 #TI1 Selection
TIM_CR2_OIS1 = 0b0000000100000000 #Output Idle state 1 (OC1 output)
TIM_CR2_OIS1N = 0b0000001000000000 #Output Idle state 1 (OC1N output)
TIM_CR2_OIS2 = 0b0000010000000000 #Output Idle state 2 (OC2 output)
TIM_CR2_OIS2N = 0b0000100000000000 #Output Idle state 2 (OC2N output)
TIM_CR2_OIS3 = 0b0001000000000000 #Output Idle state 3 (OC3 output)
TIM_CR2_OIS3N = 0b0010000000000000 #Output Idle state 3 (OC3N output)
TIM_CR2_OIS4 = 0b0100000000000000 #Output Idle state 4 (OC4 output)
TIM_SMCR_SMS = 0b0000000000000111 #[2:0] Slave mode select
TIM_SMCR_TS = 0b0000000001110000 #[2:0] Trigger selection
TIM_SMCR_MSM = 0b0000000010000000 #Master/slave mode
TIM_SMCR_ETF = 0b0000111100000000 #[3:0] External Trigger Filter
TIM_SMCR_ETPS = 0b0011000000000000 #[1:0] Extn Trig Prescalar
TIM_SMCR_ECE = 0b0100000000000000 #External clock enable
TIM_SMCR_ETP = 0b1000000000000000 #External trigger polarity
TIM_DIER_UIE = 0b0000000000000001 #Update interrupt enable
TIM_DIER_CC1IE = 0b0000000000000010 #Capture/Compare 1 interrupt enable
TIM_DIER_CC2IE = 0b0000000000000100 #Capture/Compare 2 interrupt enable
TIM_DIER_CC3IE = 0b0000000000001000 #Capture/Compare 3 interrupt enable
TIM_DIER_CC4IE = 0b0000000000010000 #Capture/Compare 4 interrupt enable
TIM_DIER_COMIE = 0b0000000000100000 #COM interrupt enable
TIM_DIER_TIE = 0b0000000001000000 #Trigger interrupt enable
TIM_DIER_BIE = 0b0000000010000000 #Break interrupt enable
TIM_DIER_UDE = 0b0000000100000000 #Update DMA request enable
TIM_DIER_CC1DE = 0b0000001000000000 #Capture/Compare 1 DMA req enable
TIM_DIER_CC2DE = 0b0000010000000000 #Capture/Compare 2 DMA req enable
TIM_DIER_CC3DE = 0b0000100000000000 #Capture/Compare 3 DMA req enable
TIM_DIER_CC4DE = 0b0001000000000000 #Capture/Compare 4 DMA req enable
TIM_DIER_COMDE = 0b0010000000000000 #COM DMA request enable
TIM_DIER_TDE = 0b0100000000000000 #Trigger DMA request enable
TIM_SR_UIF = 0b0000000000000001 #Update interrupt Flag
TIM_SR_CC1IF = 0b0000000000000010 #Capture/Compare 1 interrupt Flag
TIM_SR_CC2IF = 0b0000000000000100 #Capture/Compare 2 interrupt Flag
TIM_SR_CC3IF = 0b0000000000001000 #Capture/Compare 3 interrupt Flag
TIM_SR_CC4IF = 0b0000000000010000 #Capture/Compare 4 interrupt Flag
TIM_SR_COMIF = 0b0000000000100000 #COM interrupt Flag
TIM_SR_TIF = 0b0000000001000000 #Trigger interrupt Flag
TIM_SR_BIF = 0b0000000010000000 #Break interrupt Flag
TIM_SR_CC1OF = 0b0000001000000000 #Capture/Compare 1 Overcapture Flag
TIM_SR_CC2OF = 0b0000010000000000 #Capture/Compare 2 Overcapture Flag
TIM_SR_CC3OF = 0b0000100000000000 #Capture/Compare 3 Overcapture Flag
TIM_SR_CC4OF = 0b0001000000000000 #Capture/Compare 4 Overcapture Flag
TIM_EGR_UG = 0b0000000000000001 #Update Generation
TIM_EGR_CC1G = 0b0000000000000010 #Cap/Cmpr1 Generation
TIM_EGR_CC2G = 0b0000000000000100 #Cap/Cmpr2 Generation
TIM_EGR_CC3G = 0b0000000000001000 #Cap/Cmpr 3 Generation
TIM_EGR_CC4G = 0b0000000000010000 #Cap/Cmpr 4 Generation
TIM_EGR_COMG = 0b0000000000100000 #Cap/Cmpr Control Update Generatn
TIM_EGR_TG = 0b0000000001000000 #Trigger Generation
TIM_EGR_BG = 0b0000000010000000 #Break Generation
TIM_CCMR1_CC1S = 0b0000000000000011 #[1:0] Capture/Compare 1 Selection
TIM_CCMR1_OC1FE = 0b0000000000000100 #Output Compare 1 Fast enable
TIM_CCMR1_OC1PE = 0b0000000000001000 #Output Compare 1 Preload enable
TIM_CCMR1_OC1M = 0b0000000001110000 #[2:0] Output Compare 1 Mode
TIM_CCMR1_OC1CE = 0b0000000010000000 #Output Compare 1Clear Enable
TIM_CCMR1_CC2S = 0b0000001100000000 #[1:0] Capture/Compare 2 Sel
TIM_CCMR1_OC2FE = 0b0000010000000000 #Output Compare 2 Fast enable
TIM_CCMR1_OC2PE = 0b0000100000000000 #Output Compare 2 Preload enable
TIM_CCMR1_OC2M = 0b0111000000000000 #[2:0] Output Compare 2 Mode
TIM_CCMR1_OC2CE = 0b1000000000000000 #Output Compare 2 Clear Enable
TIM_CCMR1_IC1PSC = 0b0000000000001100 #[1:0] Input Capture 1 Prescaler
TIM_CCMR1_IC1F = 0b0000000011110000 #[3:0] Input Capture 1 Filter
TIM_CCMR1_IC2PSC = 0b0000110000000000 #[1:0] Input Capture 2 Prescaler
TIM_CCMR1_IC2F = 0b1111000000000000 #[3:0] Input Capture 2 Filter
TIM_CCMR2_CC3S = 0b0000000000000011 #[1:0] Capture/Compare 3 Selectio
TIM_CCMR2_OC3FE = 0b0000000000000100 #Output Compare 3 Fast enable
TIM_CCMR2_OC3PE = 0b0000000000001000 #Output Compare 3 Preload enable
TIM_CCMR2_OC3M = 0b0000000001110000 #[2:0] Output Compare 3 Mode
TIM_CCMR2_OC3CE = 0b0000000010000000 #Output Compare 3 Clear Enable
TIM_CCMR2_CC4S = 0b0000001100000000 #[1:0] Capture/Compare 4 Seln
TIM_CCMR2_OC4FE = 0b0000010000000000 #Output Compare 4 Fast enable
TIM_CCMR2_OC4PE = 0b0000100000000000 #Output Compare 4 Preload enable
TIM_CCMR2_OC4M = 0b0111000000000000 #[2:0] Output Compare 4 Mode
TIM_CCMR2_OC4CE = 0b1000000000000000 #Output Compare 4 Clear Enable
TIM_CCMR2_IC3PSC = 0b0000000000001100 #[1:0] Input Capture 3 Prescaler
TIM_CCMR2_IC3F = 0b0000000011110000 #[3:0] Input Capture 3 Filter
TIM_CCMR2_IC4PSC = 0b0000110000000000 #[1:0] Input Capture 4 Prescaler
TIM_CCMR2_IC4F = 0b1111000000000000 #[3:0] Input Capture 4 Filter
TIM_CCER_CC1E = 0b0000000000000001 #Cap/Cmpr 1 output enable
TIM_CCER_CC1P = 0b0000000000000010 #Cap/Cmpr 1 output Polarity
TIM_CCER_CC1NE = 0b0000000000000100 #Cap/Cmpr 1 Complementary out enbl
TIM_CCER_CC1NP = 0b0000000000001000 #Cap/Cmpr 1 Complementary out pol
TIM_CCER_CC2E = 0b0000000000010000 #Cap/Cmpr 2 output enable
TIM_CCER_CC2P = 0b0000000000100000 #Cap/Cmpr 2 output Polarity
TIM_CCER_CC2NE = 0b0000000001000000 #Cap/Cmpr 2 Complementary out enbl
TIM_CCER_CC2NP = 0b0000000010000000 #Cap/Cmpr 2 Complementary out pol
TIM_CCER_CC3E = 0b0000000100000000 #Cap/Cmpr 3 output enable
TIM_CCER_CC3P = 0b0000001000000000 #Cap/Cmpr 3 output Polarity
TIM_CCER_CC3NE = 0b0000010000000000 #Cap/Cmpr 3 Complementary out enbl
TIM_CCER_CC3NP = 0b0000100000000000 #Cap/Cmpr 3 Complementary out pol
TIM_CCER_CC4E = 0b0001000000000000 #Cap/Cmpr 4 output enable
TIM_CCER_CC4P = 0b0010000000000000 #Cap/Cmpr 4 output Polarity
TIM_CCER_CC4NP = 0b0100000000000000 #Cap/Cmpr 4 Complementary out pol
TIM_BDTR_DTG = 0b0000000011111111 #[0:7] Dead-Time Generator set-up
TIM_BDTR_LOCK = 0b0000001100000000 #[1:0] Lock Configuration
TIM_BDTR_OSSI = 0b0000010000000000 #Off-State Selection for Idle mode
TIM_BDTR_OSSR = 0b0000100000000000 #Off-State Selection for Run mode
TIM_BDTR_BKE = 0b0001000000000000 #Break enable
TIM_BDTR_BKP = 0b0010000000000000 #Break Polarity
TIM_BDTR_AOE = 0b0100000000000000 #Automatic Output enable
TIM_BDTR_MOE = 0b1000000000000000 #Main Output enable
TIM_DCR_DBA = 0b0000000000011111 #[4:0] DMA Base Address
TIM_DCR_DBL = 0b0001111100000000 #[4:0] DMA Burst Length
TIM_OR_TI4_RMP = 0b0000000011000000 #[1:0] TIM5 Input 4 remap
TIM_OR_ITR1_RMP = 0b0000110000000000 #[1:0] TIM2 Intrnl trigger 1 remap