platforms/boards/pyboard/stm opmasks rcc
RCC_CR_HSITRIM = 0x000000F8
RCC_CR_HSICAL = 0x0000FF00
RCC_CR_HSEON = 0x00010000
RCC_CR_HSERDY = 0x00020000
RCC_CR_HSEBYP = 0x00040000
RCC_CR_CSSON = 0x00080000
RCC_CR_PLLON = 0x01000000
RCC_CR_PLLRDY = 0x02000000
RCC_CR_PLLI2SON = 0x04000000
RCC_CR_PLLI2SRDY = 0x08000000
#Bit definition for RCC_PLLCFGR register
RCC_PLLCFGR_PLLM = 0x0000003F
RCC_PLLCFGR_PLLM_0 = 0x00000001
RCC_PLLCFGR_PLLM_1 = 0x00000002
RCC_PLLCFGR_PLLM_2 = 0x00000004
RCC_PLLCFGR_PLLM_3 = 0x00000008
RCC_PLLCFGR_PLLM_4 = 0x00000010
RCC_PLLCFGR_PLLM_5 = 0x00000020
RCC_PLLCFGR_PLLN = 0x00007FC0
RCC_PLLCFGR_PLLN_0 = 0x00000040
RCC_PLLCFGR_PLLN_1 = 0x00000080
RCC_PLLCFGR_PLLN_2 = 0x00000100
RCC_PLLCFGR_PLLN_3 = 0x00000200
RCC_PLLCFGR_PLLN_4 = 0x00000400
RCC_PLLCFGR_PLLN_5 = 0x00000800
RCC_PLLCFGR_PLLN_6 = 0x00001000
RCC_PLLCFGR_PLLN_7 = 0x00002000
RCC_PLLCFGR_PLLN_8 = 0x00004000
RCC_PLLCFGR_PLLP = 0x00030000
RCC_PLLCFGR_PLLP_0 = 0x00010000
RCC_PLLCFGR_PLLP_1 = 0x00020000
RCC_PLLCFGR_PLLSRC = 0x00400000
RCC_PLLCFGR_PLLSRC_HSE = 0x00400000
RCC_PLLCFGR_PLLSRC_HSI = 0x00000000
RCC_PLLCFGR_PLLQ = 0x0F000000
RCC_PLLCFGR_PLLQ_0 = 0x01000000
RCC_PLLCFGR_PLLQ_1 = 0x02000000
RCC_PLLCFGR_PLLQ_2 = 0x04000000
RCC_PLLCFGR_PLLQ_3 = 0x08000000
#Bit definition for RCC_CFGR register / SW configuration
RCC_CFGR_SW = 0x00000003 #[1:0] bits (System clock Switch)
RCC_CFGR_SW_HSI = 0x00000000 #HSI selected as system clock
RCC_CFGR_SW_HSE = 0x00000001 #HSE selected as system clock
RCC_CFGR_SW_PLL = 0x00000002 #PLL selected as system clock
#SWS configuration
RCC_CFGR_SWS = 0x0000000C #[1:0] bits (System Clock Switch Status)
RCC_CFGR_SWS_HSI = 0x00000000 #HSI oscillator used as system clock
RCC_CFGR_SWS_HSE = 0x00000004 #HSE oscillator used as system clock
RCC_CFGR_SWS_PLL = 0x00000008 #PLL used as system clock
#HPRE configuration
RCC_CFGR_HPRE = 0x000000F0 #[3:0] bits (AHB prescaler)
RCC_CFGR_HPRE_DIV1 = 0x00000000 #SYSCLK not divided
RCC_CFGR_HPRE_DIV2 = 0x00000080 #SYSCLK divided by 2
RCC_CFGR_HPRE_DIV4 = 0x00000090 #SYSCLK divided by 4
RCC_CFGR_HPRE_DIV8 = 0x000000A0 #SYSCLK divided by 8
RCC_CFGR_HPRE_DIV16 = 0x000000B0 #SYSCLK divided by 16
RCC_CFGR_HPRE_DIV64 = 0x000000C0 #SYSCLK divided by 64
RCC_CFGR_HPRE_DIV128 = 0x000000D0 #SYSCLK divided by 128
RCC_CFGR_HPRE_DIV256 = 0x000000E0 #SYSCLK divided by 256
RCC_CFGR_HPRE_DIV512 = 0x000000F0 #SYSCLK divided by 512
#PPRE1 configuration
RCC_CFGR_PPRE1 = 0x00001C00 #[2:0] bits (APB1 prescaler)
RCC_CFGR_PPRE1_DIV1 = 0x00000000 #HCLK not divided
RCC_CFGR_PPRE1_DIV2 = 0x00001000 #HCLK divided by 2
RCC_CFGR_PPRE1_DIV4 = 0x00001400 #HCLK divided by 4
RCC_CFGR_PPRE1_DIV8 = 0x00001800 #HCLK divided by 8
RCC_CFGR_PPRE1_DIV16 = 0x00001C00 #HCLK divided by 16
#PPRE2 configuration
RCC_CFGR_PPRE2 = 0x0000E000 #[2:0] bits (APB2 prescaler)
RCC_CFGR_PPRE2_DIV1 = 0x00000000 #HCLK not divided
RCC_CFGR_PPRE2_DIV2 = 0x00008000 #HCLK divided by 2
RCC_CFGR_PPRE2_DIV4 = 0x0000A000 #HCLK divided by 4
RCC_CFGR_PPRE2_DIV8 = 0x0000C000 #HCLK divided by 8
RCC_CFGR_PPRE2_DIV16 = 0x0000E000 #HCLK divided by 16
#RTCPRE configuration
RCC_CFGR_RTCPRE = 0x001F0000
RCC_CFGR_RTCPRE_0 = 0x00010000
RCC_CFGR_RTCPRE_1 = 0x00020000
RCC_CFGR_RTCPRE_2 = 0x00040000
RCC_CFGR_RTCPRE_3 = 0x00080000
RCC_CFGR_RTCPRE_4 = 0x00100000
#MCO1 configuration
RCC_CFGR_MCO1 = 0x00600000
RCC_CFGR_MCO1_0 = 0x00200000
RCC_CFGR_MCO1_1 = 0x00400000
RCC_CFGR_I2SSRC = 0x00800000
RCC_CFGR_MCO1PRE = 0x07000000
RCC_CFGR_MCO1PRE_0 = 0x01000000
RCC_CFGR_MCO1PRE_1 = 0x02000000
RCC_CFGR_MCO1PRE_2 = 0x04000000
RCC_CFGR_MCO2PRE = 0x38000000
RCC_CFGR_MCO2PRE_0 = 0x08000000
RCC_CFGR_MCO2PRE_1 = 0x10000000
RCC_CFGR_MCO2PRE_2 = 0x20000000
RCC_CFGR_MCO2 = 0xC0000000
RCC_CFGR_MCO2_0 = 0x40000000
RCC_CFGR_MCO2_1 = 0x80000000
#Bit definition for RCC_CIR register
RCC_CIR_LSIRDYF = 0x00000001
RCC_CIR_LSERDYF = 0x00000002
RCC_CIR_HSIRDYF = 0x00000004
RCC_CIR_HSERDYF = 0x00000008
RCC_CIR_PLLRDYF = 0x00000010
RCC_CIR_PLLI2SRDYF = 0x00000020
RCC_CIR_CSSF = 0x00000080
RCC_CIR_LSIRDYIE = 0x00000100
RCC_CIR_LSERDYIE = 0x00000200
RCC_CIR_HSIRDYIE = 0x00000400
RCC_CIR_HSERDYIE = 0x00000800
RCC_CIR_PLLRDYIE = 0x00001000
RCC_CIR_PLLI2SRDYIE = 0x00002000
RCC_CIR_LSIRDYC = 0x00010000
RCC_CIR_LSERDYC = 0x00020000
RCC_CIR_HSIRDYC = 0x00040000
RCC_CIR_HSERDYC = 0x00080000
RCC_CIR_PLLRDYC = 0x00100000
RCC_CIR_PLLI2SRDYC = 0x00200000
RCC_CIR_CSSC = 0x00800000
#Bit definition for RCC_AHB1RSTR register
RCC_AHB1RSTR_GPIOARST = 0x00000001
RCC_AHB1RSTR_GPIOBRST = 0x00000002
RCC_AHB1RSTR_GPIOCRST = 0x00000004
RCC_AHB1RSTR_GPIODRST = 0x00000008
RCC_AHB1RSTR_GPIOERST = 0x00000010
RCC_AHB1RSTR_GPIOFRST = 0x00000020
RCC_AHB1RSTR_GPIOGRST = 0x00000040
RCC_AHB1RSTR_GPIOHRST = 0x00000080
RCC_AHB1RSTR_GPIOIRST = 0x00000100
RCC_AHB1RSTR_CRCRST = 0x00001000
RCC_AHB1RSTR_DMA1RST = 0x00200000
RCC_AHB1RSTR_DMA2RST = 0x00400000
RCC_AHB1RSTR_OTGHRST = 0x10000000
#Bit definition for RCC_AHB2RSTR register
RCC_AHB2RSTR_RNGRST = 0x00000040
RCC_AHB2RSTR_OTGFSRST = 0x00000080
#Bit definition for RCC_AHB3RSTR register
RCC_AHB3RSTR_FSMCRST = 0x00000001
#Bit definition for RCC_APB1RSTR register
RCC_APB1RSTR_TIM2RST = 0x00000001
RCC_APB1RSTR_TIM3RST = 0x00000002
RCC_APB1RSTR_TIM4RST = 0x00000004
RCC_APB1RSTR_TIM5RST = 0x00000008
RCC_APB1RSTR_TIM6RST = 0x00000010
RCC_APB1RSTR_TIM7RST = 0x00000020
RCC_APB1RSTR_TIM12RST = 0x00000040
RCC_APB1RSTR_TIM13RST = 0x00000080
RCC_APB1RSTR_TIM14RST = 0x00000100
RCC_APB1RSTR_WWDGRST = 0x00000800
RCC_APB1RSTR_SPI2RST = 0x00004000
RCC_APB1RSTR_SPI3RST = 0x00008000
RCC_APB1RSTR_USART2RST = 0x00020000
RCC_APB1RSTR_USART3RST = 0x00040000
RCC_APB1RSTR_UART4RST = 0x00080000
RCC_APB1RSTR_UART5RST = 0x00100000
RCC_APB1RSTR_I2C1RST = 0x00200000
RCC_APB1RSTR_I2C2RST = 0x00400000
RCC_APB1RSTR_I2C3RST = 0x00800000
RCC_APB1RSTR_CAN1RST = 0x02000000
RCC_APB1RSTR_CAN2RST = 0x04000000
RCC_APB1RSTR_PWRRST = 0x10000000
RCC_APB1RSTR_DACRST = 0x20000000
#Bit definition for RCC_APB2RSTR register
RCC_APB2RSTR_TIM1RST = 0x00000001
RCC_APB2RSTR_TIM8RST = 0x00000002
RCC_APB2RSTR_USART1RST = 0x00000010
RCC_APB2RSTR_USART6RST = 0x00000020
RCC_APB2RSTR_ADCRST = 0x00000100
RCC_APB2RSTR_SDIORST = 0x00000800
RCC_APB2RSTR_SPI1RST = 0x00001000
RCC_APB2RSTR_SYSCFGRST = 0x00004000
RCC_APB2RSTR_TIM9RST = 0x00010000
RCC_APB2RSTR_TIM10RST = 0x00020000
RCC_APB2RSTR_TIM11RST = 0x00040000
#Bit definition for RCC_AHB1ENR register
RCC_AHB1ENR_GPIOAEN = 0x00000001
RCC_AHB1ENR_GPIOBEN = 0x00000002
RCC_AHB1ENR_GPIOCEN = 0x00000004
RCC_AHB1ENR_GPIODEN = 0x00000008
RCC_AHB1ENR_GPIOEEN = 0x00000010
RCC_AHB1ENR_GPIOFEN = 0x00000020
RCC_AHB1ENR_GPIOGEN = 0x00000040
RCC_AHB1ENR_GPIOHEN = 0x00000080
RCC_AHB1ENR_GPIOIEN = 0x00000100
RCC_AHB1ENR_CRCEN = 0x00001000
RCC_AHB1ENR_BKPSRAMEN = 0x00040000
RCC_AHB1ENR_CCMDATARAMEN = 0x00100000
RCC_AHB1ENR_DMA1EN = 0x00200000
RCC_AHB1ENR_DMA2EN = 0x00400000
RCC_AHB1ENR_OTGHSEN = 0x20000000
RCC_AHB1ENR_OTGHSULPIEN = 0x40000000
#Bit definition for RCC_AHB2ENR register
RCC_AHB2ENR_RNGEN = 0x00000040
RCC_AHB2ENR_OTGFSEN = 0x00000080
#Bit definition for RCC_AHB3ENR register
RCC_AHB3ENR_FSMCEN = 0x00000001
#Bit definition for RCC_APB1ENR register
RCC_APB1ENR_TIM2EN = 0x00000001
RCC_APB1ENR_TIM3EN = 0x00000002
RCC_APB1ENR_TIM4EN = 0x00000004
RCC_APB1ENR_TIM5EN = 0x00000008
RCC_APB1ENR_TIM6EN = 0x00000010
RCC_APB1ENR_TIM7EN = 0x00000020
RCC_APB1ENR_TIM12EN = 0x00000040
RCC_APB1ENR_TIM13EN = 0x00000080
RCC_APB1ENR_TIM14EN = 0x00000100
RCC_APB1ENR_WWDGEN = 0x00000800
RCC_APB1ENR_SPI2EN = 0x00004000
RCC_APB1ENR_SPI3EN = 0x00008000
RCC_APB1ENR_USART2EN = 0x00020000
RCC_APB1ENR_USART3EN = 0x00040000
RCC_APB1ENR_UART4EN = 0x00080000
RCC_APB1ENR_UART5EN = 0x00100000
RCC_APB1ENR_I2C1EN = 0x00200000
RCC_APB1ENR_I2C2EN = 0x00400000
RCC_APB1ENR_I2C3EN = 0x00800000
RCC_APB1ENR_CAN1EN = 0x02000000
RCC_APB1ENR_CAN2EN = 0x04000000
RCC_APB1ENR_PWREN = 0x10000000
RCC_APB1ENR_DACEN = 0x20000000
#Bit definition for RCC_APB2ENR register
RCC_APB2ENR_TIM1EN = 0x00000001
RCC_APB2ENR_TIM8EN = 0x00000002
RCC_APB2ENR_USART1EN = 0x00000010
RCC_APB2ENR_USART6EN = 0x00000020
RCC_APB2ENR_ADC1EN = 0x00000100
RCC_APB2ENR_ADC2EN = 0x00000200
RCC_APB2ENR_ADC3EN = 0x00000400
RCC_APB2ENR_SDIOEN = 0x00000800
RCC_APB2ENR_SPI1EN = 0x00001000
RCC_APB2ENR_SYSCFGEN = 0x00004000
RCC_APB2ENR_TIM9EN = 0x00010000
RCC_APB2ENR_TIM10EN = 0x00020000
RCC_APB2ENR_TIM11EN = 0x00040000
RCC_APB2ENR_SPI5EN = 0x00100000
RCC_APB2ENR_SPI6EN = 0x00200000
#Bit definition for RCC_AHB1LPENR register
RCC_AHB1LPENR_GPIOALPEN = 0x00000001
RCC_AHB1LPENR_GPIOBLPEN = 0x00000002
RCC_AHB1LPENR_GPIOCLPEN = 0x00000004
RCC_AHB1LPENR_GPIODLPEN = 0x00000008
RCC_AHB1LPENR_GPIOELPEN = 0x00000010
RCC_AHB1LPENR_GPIOFLPEN = 0x00000020
RCC_AHB1LPENR_GPIOGLPEN = 0x00000040
RCC_AHB1LPENR_GPIOHLPEN = 0x00000080
RCC_AHB1LPENR_GPIOILPEN = 0x00000100
RCC_AHB1LPENR_CRCLPEN = 0x00001000
RCC_AHB1LPENR_FLITFLPEN = 0x00008000
RCC_AHB1LPENR_SRAM1LPEN = 0x00010000
RCC_AHB1LPENR_SRAM2LPEN = 0x00020000
RCC_AHB1LPENR_BKPSRAMLPEN = 0x00040000
RCC_AHB1LPENR_SRAM3LPEN = 0x00080000
RCC_AHB1LPENR_DMA1LPEN = 0x00200000
RCC_AHB1LPENR_DMA2LPEN = 0x00400000
RCC_AHB1LPENR_OTGHSLPEN = 0x20000000
RCC_AHB1LPENR_OTGHSULPILPEN = 0x40000000
#Bit definition for RCC_AHB2LPENR register
RCC_AHB2LPENR_RNGLPEN = 0x00000040
RCC_AHB2LPENR_OTGFSLPEN = 0x00000080
#Bit definition for RCC_AHB3LPENR register
RCC_AHB3LPENR_FSMCLPEN = 0x00000001
#Bit definition for RCC_APB1LPENR register
RCC_APB1LPENR_TIM2LPEN = 0x00000001
RCC_APB1LPENR_TIM3LPEN = 0x00000002
RCC_APB1LPENR_TIM4LPEN = 0x00000004
RCC_APB1LPENR_TIM5LPEN = 0x00000008
RCC_APB1LPENR_TIM6LPEN = 0x00000010
RCC_APB1LPENR_TIM7LPEN = 0x00000020
RCC_APB1LPENR_TIM12LPEN = 0x00000040
RCC_APB1LPENR_TIM13LPEN = 0x00000080
RCC_APB1LPENR_TIM14LPEN = 0x00000100
RCC_APB1LPENR_WWDGLPEN = 0x00000800
RCC_APB1LPENR_SPI2LPEN = 0x00004000
RCC_APB1LPENR_SPI3LPEN = 0x00008000
RCC_APB1LPENR_USART2LPEN = 0x00020000
RCC_APB1LPENR_USART3LPEN = 0x00040000
RCC_APB1LPENR_UART4LPEN = 0x00080000
RCC_APB1LPENR_UART5LPEN = 0x00100000
RCC_APB1LPENR_I2C1LPEN = 0x00200000
RCC_APB1LPENR_I2C2LPEN = 0x00400000
RCC_APB1LPENR_I2C3LPEN = 0x00800000
RCC_APB1LPENR_CAN1LPEN = 0x02000000
RCC_APB1LPENR_CAN2LPEN = 0x04000000
RCC_APB1LPENR_PWRLPEN = 0x10000000
RCC_APB1LPENR_DACLPEN = 0x20000000
#Bit definition for RCC_APB2LPENR register
RCC_APB2LPENR_TIM1LPEN = 0x00000001
RCC_APB2LPENR_TIM8LPEN = 0x00000002
RCC_APB2LPENR_USART1LPEN = 0x00000010
RCC_APB2LPENR_USART6LPEN = 0x00000020
RCC_APB2LPENR_ADC1LPEN = 0x00000100
RCC_APB2LPENR_ADC2LPEN = 0x00000200
RCC_APB2LPENR_ADC3LPEN = 0x00000400
RCC_APB2LPENR_SDIOLPEN = 0x00000800
RCC_APB2LPENR_SPI1LPEN = 0x00001000
RCC_APB2LPENR_SYSCFGLPEN = 0x00004000
RCC_APB2LPENR_TIM9LPEN = 0x00010000
RCC_APB2LPENR_TIM10LPEN = 0x00020000
RCC_APB2LPENR_TIM11LPEN = 0x00040000
#Bit definition for RCC_BDCR register
RCC_BDCR_LSEON = 0x00000001
RCC_BDCR_LSERDY = 0x00000002
RCC_BDCR_LSEBYP = 0x00000004
RCC_BDCR_RTCSEL = 0x00000300
RCC_BDCR_RTCSEL_0 = 0x00000100
RCC_BDCR_RTCSEL_1 = 0x00000200
RCC_BDCR_RTCEN = 0x00008000
RCC_BDCR_BDRST = 0x00010000
#Bit definition for RCC_CSR register
RCC_CSR_LSION = 0x00000001
RCC_CSR_LSIRDY = 0x00000002
RCC_CSR_RMVF = 0x01000000
RCC_CSR_BORRSTF = 0x02000000
RCC_CSR_PADRSTF = 0x04000000
RCC_CSR_PORRSTF = 0x08000000
RCC_CSR_SFTRSTF = 0x10000000
RCC_CSR_WDGRSTF = 0x20000000
RCC_CSR_WWDGRSTF = 0x40000000
RCC_CSR_LPWRRSTF = 0x80000000
#Bit definition for RCC_SSCGR register
RCC_SSCGR_MODPER = 0x00001FFF
RCC_SSCGR_INCSTEP = 0x0FFFE000
RCC_SSCGR_SPREADSEL = 0x40000000
RCC_SSCGR_SSCGEN = 0x80000000
#Bit definition for RCC_PLLI2SCFGR register
RCC_PLLI2SCFGR_PLLI2SN = 0x00007FC0
RCC_PLLI2SCFGR_PLLI2SN_0 = 0x00000040
RCC_PLLI2SCFGR_PLLI2SN_1 = 0x00000080
RCC_PLLI2SCFGR_PLLI2SN_2 = 0x00000100
RCC_PLLI2SCFGR_PLLI2SN_3 = 0x00000200
RCC_PLLI2SCFGR_PLLI2SN_4 = 0x00000400
RCC_PLLI2SCFGR_PLLI2SN_5 = 0x00000800
RCC_PLLI2SCFGR_PLLI2SN_6 = 0x00001000
RCC_PLLI2SCFGR_PLLI2SN_7 = 0x00002000
RCC_PLLI2SCFGR_PLLI2SN_8 = 0x00004000
RCC_PLLI2SCFGR_PLLI2SR = 0x70000000
RCC_PLLI2SCFGR_PLLI2SR_0 = 0x10000000
RCC_PLLI2SCFGR_PLLI2SR_1 = 0x20000000
RCC_PLLI2SCFGR_PLLI2SR_2 = 0x40000000